The present invention relates generally to high-frequency digital communications systems, and more specifically to a frequency discrimination technique for a PSK (phase shift keyed) modulation system operating in the Gigahertz band and to an automatic frequency tracking circuit utilizing the discrimination technique.
With systems operating in the Gigahertz band such as satellite and mobile communications systems, frequency conversion processes at various stages of the transmission route and the Doppler shift caused by the movement of satellite and mobile stations often result in a substantial amount of frequency variation. Particularly in the case of mobile systems, the maximum frequency shift of PSK modulation would become equal to or greater than the highest frequency of the modulating signal.
According to the prior art frequency compensation technique, an automatic frequency tracking circuit is employed in a stage prior to the stage of demodulation. The tracking circuit includes a frequency discriminator that extracts information representing the frequency deviation of the transmitted carrier from received signal and uses it to control the voltage-controlled oscillator of a phase-locked loop.
Frequency discriminators of the cross product type are well known and have been extensively uses. As described in "AFC Tracking Algorithms," F. D. Natali, IEEE Transactions On Communications, Vol. COM 32, No. 8, Aug. 1984, Pages 935 to 947, the discriminator includes a pair of delay circuits, a pair of multipliers and a subtracter. The real part and imaginary part of quasi-coherently detected orthogonal (complex) signals are applied respectively to the delay circuits in which they are delayed so that the real and imaginary parts are respectively time coincident with the imaginary part and the real part at the inputs of the multipliers. The nondelayed versions of the real and imaginary parts are cross-coupled to the multipliers in which they are multiplied with the delayed signals. The outputs of the multipliers are fed to the subtracter to detect the frequency variation of the received signal. Let r(t) denote the quasi-coherently detected orthogonal signals and let .DELTA.f denote the frequency variation of the received signal, the following is obtained: EQU r(t)=[p(t)+jq(t)]exp(j2.pi..DELTA.ft)
where, p(t) and p(t) represent respectively the real and imaginary parts of the complex signals. The output of the cross product discriminator d(t) is then given by: EQU d(t)=[p(t)p(t-T)+q(t)q(t-T)] sin (2.pi..DELTA.fT)+[q(t)p(t-T)-p(t)q(t-T)] cos (2.pi..DELTA.fT) (1)
where T is the delay time introduced by each of the delay circuits. If the symbol (clock) period of the received signal is sufficiently smaller than the delay time T, the polarity of the value in the brackets of the first term of Equation (1) is always positive and the frequency variation is represented by the sin (2.pi..DELTA.fT) of the first term. On the other hand, the second term of the equation assumes a random value depending on the modulation patterns of the components p(t) and q(t), resulting in the generation of undesired pattern dependent jitter, except for BPSK (biphase shift keyed) signals in which the second term is zero since p(t)=q(t).
In an automatic frequency control loop, a sampler is used for sampling the complex signals at instants 1/2 of the clock period and a modulation remover is connected to the output of the sampler for removing modulation by the use of frequency multiplication technique prior to coupling to the cross-product discriminator. The output of the discriminator is coupled through a loop filter to a voltage-controlled oscillator which generates quadrature carriers with which the complex signals are multiplied to compensate for a frequency variation. In this case, the output r(t) of the modulation remover and the output d(nT) of the discriminator are given by: EQU r(t)=exp (j2.pi.M.DELTA.fT) EQU d(nT)=sin (2.pi.M.DELTA.fT)
where, M represents the number of phases of the PSK signal and n is an integer. The pull-in range of frequency variations that can be locked must be smaller than f.sub.s /2M, where f.sub.s is the clock frequency. Therefore, as the number of modulation phases increases, the pull-in range becomes narrow. Another disadvantage is that at low signal to noise ratios the nonlinearity loss due to frequency multiplication becomes substantial.